Home > Sony Vaio > SONY VAIO LAPTOP PLL FOUND :) Yay

SONY VAIO LAPTOP PLL FOUND :) Yay

Signed-off-by: Xiong Zhang Reviewed-by: Rodrigo Vivi Tested-by: Timo Aaltonen Signed-off-by: Jani Nikula /linux/stable/drivers/gpu/drm/i915/i915_drv.h /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_display.c /linux/stable/drivers/gpu/drm/i915/intel_dp.c /linux/stable/drivers/gpu/drm/i915/intel_hotplug.c 3774eb507e7b7df7f9b7d8d867eea330c7146aaa 10-Aug-2015 Paulo Zanoni drm/i915: fix stolen bios_reserved v7: There is no need to update the pml4 register value in execlists_update_context. (Akash) v8: Move pd and pdp setup functions to a previous patch, they do not belong here. (Akash) To work around this we simply check for the 0 value of the CL2 register (which is what we get when it's powered down) and adjust our expectations. v2: - s/BIOS reserved/stolen reserved/g (Chris) - Don't DRM_ERROR if we can't do anything about it (Chris) - Improve debug messages (Chris). - Use the gen7 version instead of gen6 on http://webcomputerrepair.com/sony-vaio/sony-vaio-operating-system-not-found-fix.html

Also, the registers are used in case control pin indicates display DDI. Fixed the macros to get proper port offsets. Also store it in kHz under dev_priv like we do for cdlck since it's not just an rps related clock, and having it in kHz is more standard/convenient for some things. Since the actual programming is very similar to the CHV/VLV DPIO PLL programming we can reuse much of the logic from there. https://www.vistax64.com/general-discussion/277042-sony-vaio-laptop-pll-found-yay.html

There is one exception for CL2 that will be dealt in a separate patch for clarity. Additionally the common lanes will power down when not needed. It creates a fixed register set that is programmed across the different engines so that all engines have the same table. Select divide by 2 option to get < 20Mhz for Tx clock 3.

  1. v4: Addressed Jani's review comments.
  2. The registers are double buffered but apparently they update on the vblank of any active pipe.
  3. v6: Update comment describing intel_guc_ucode_load() [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai Signed-off-by: Dave Gordon Reviewed-by: Tom O'Rourke Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/Makefile /linux/stable/drivers/gpu/drm/i915/i915_dma.c /linux/stable/drivers/gpu/drm/i915/i915_drv.h /linux/stable/drivers/gpu/drm/i915/i915_gem.c /linux/stable/drivers/gpu/drm/i915/i915_guc_reg.h /linux/stable/drivers/gpu/drm/i915/i915_reg.h
  4. But we can of course poll until the expected value appears.

Reviewed-by: Paulo Zanoni Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 195baa0673345c70f04d19e9e18470c9cbf88bcf 27-Aug-2015 Ville Syrjälä drm/i915: Rename BXT PORTA HPD defines The PORTA HPD defines are not This one was added on GEN2, where it was the only INSTDONE register, so mark it as such. The set of MOCS configuration entries introduced by this patch is intended to be minimal but sufficient to cover the needs of current userspace - i.e. It shouldn't be too long so this shouldn't make modesets substantially longer.

This is now updated with correct length and moved to appropriate place. If root cause for system hang is found and can be worked around with another means, we can reconsider if we can reinstate full reset for unreadiness case. Also save/restore only as many SWF registers that each platform has. https://esupport.sony.com/US/p/model-home.pl?mdl=VGNFZ220E v2: Fixed Jani's review comments.

Suggested by Ville. v2: Fix SPT and VLV. In this setup, userspace should only utilize the first N entries, higher entries are reserved for future use. v2: Rebased due to crtc->config changes s/HDMI_GC/HDMIUNIT_GC/ to match spec better Factor out intel_enable_hdmi_audio() Signed-off-by: Ville Syrjälä Reviewed-by: Ander Conselvan de Oliveira Reviewed-By: Chandra Konduru Testecase: igt/kms_render/* Signed-off-by:

Cc: Chris Wilson Cc: Dave Gordon Signed-off-by: Arun Siluvery Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_cmd_parser.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_lrc.c 4c436d55b279bbc6b02aac02e7dc683fc09f884e 16-Jun-2015 Abdiel Janulgue drm/i915: Enable Resource Added check for ULPS mode(No effects on VLV). 2. tab issues. Or at least I assume those were meant to be hex numbers.

By inspecting the unreadiness for reset seems to correlate with the probable system hang. this content Notice that since this is always dealing with the top of the stolen memory, the problems are not so easy to reproduce - especially since FBC is still disabled by default. Fixed Jani's review comments. To construct the expected value we look at our shadow PHY_CONTROL register value (which should match what we've just written to the hardware), and we also need to look at the

to make it clear they apply to all CCK clock control registers. v4: - Code formatting. (Chris Wilson) - re-privatised mocs code. (Daniel Vetter) v5: - Changed the name of a function. (Chris Wilson) v6: - re-based - Added Mesa table entry (skylake After that, I noticed that the reserved area has a specific start, and may not exactly end where the stolen memory ends. http://webcomputerrepair.com/sony-vaio/sony-vaio-laptop-not-detecting-wifi.html enable_dsi_pll function.

This patch may solve random stolen memory corruption/problems on almost all platforms. MIPI device ready changes to support dsi_pre_enable. Signed-off-by: Imre Deak Reviewed-by: Sonika Jindal Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 6381b55016ec76f18cbc8685ca0774dd4584651b 14-Jul-2015 Nick Hoath drm/i915/gen9: Implement WaDisableKillLogic for gen 9 v2: Patch leakage fixed Signed-off-by: Nick

With potentially some lanes powered down, the DP code now has to check the number of active lanes before accessing PCS/TX registers.

This information is based on available counts but takes power gated slices into account. When the port is disabled the power down override is not needed and the lanes will shut off on their own. Move lane_count into pipe_config to avoid that. v2: rebase Cc: Dave Gordon Signed-off-by: Arun Siluvery Reviewed-by: Mika Kuoppala [danvet: Appease checkpatch as Mika spotted in i915_reg.h - it seems terminally unhappy about i915_cmd_parser.c so that

Adjusted the Macro definition as per convention. This can be confusing when comparing two parts of the code accessing the register via different names. They also exist on SPT, and partially already on LPT:LP. http://webcomputerrepair.com/sony-vaio/sony-vaio-laptop-not-booting-up-windows-8-8-1.html Dave identified an issue with the current implementation where the register value is read once at the beginning and it is reused; this patch corrects this by saving the register value

They are: 1. Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_runtime_pm.c 6669e39f95b5530ca8cb9137703ceb5e83e5d648 08-Jul-2015 Ville Syrjälä drm/i915: Add some CHV DPIO lane power state asserts Add some checks Reviewed-by: Paulo Zanoni Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 40bfd7a3303b7c383493c80a250c59b61d812ce5 27-Aug-2015 Ville Syrjälä drm/i915: Clean up various HPD defines Indent the PORTx_HOTPLUG_... v2: PML4 update in legacy context switch is left for historic reasons, the preferred mode of operation is with lrc context based submission.

Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h 699fc401da1c9cc8c6bda578ca3d6310924276a2 18-Sep-2015 Ville Syrjälä drm/i915: Include gpio_mmio_base in GMBUS reg defines Signed-off-by: Ville Syrjälä Reviewed-by: Jesse The hardware only provides two bits per channel indicating whether all or some of the lanes are powered down, so we can't do an exact check. So add the code to decode it. Reviewed-by: Chris Wilson Signed-off-by: Abdiel Janulgue Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_ringbuffer.c /linux/stable/drivers/gpu/drm/i915/intel_ringbuffer.h e62925567c7926e78bc8ca976cde5c28ea265a49 01-Jul-2015 Vandana Kannan drm/i915/bxt: BUNs related to port PLL This patch contains changes based

Note that there is also a GEN2 version of this register, but that's on a different address so not handled in this patch. Cc: Clint Taylor Signed-off-by: Jani Nikula Reviewed-by: Clint Taylor Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_drv.h /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_panel.c a52bb15bfad09115cff2433e76b164be94c42af5 27-Aug-2015 Ville Syrjälä drm/i915: Rewrite BXT HPD code to conform By only looking at the size we were assuming that the reserved area was always at the very top of stolen, which is not always true. a good set of defaults.

Also sprinkle a few debug prints around so that we can monitor the DISPLAY_PHY_STATUS changes without having to read it and risk corrupting it. For sinks that don't support deep color let's skip the GCP in case it might confuse the sink, although HDMI 1.4 spec does say all sinks must be capable of reciving Keep the original name with a platform prefix to make it clearer which INSTDONE register instance this is. Added checks for enabled slices, subslices and EU for Broadwell.

{Code Search Cross Reference: i915_reg.h xref: /linux/stable/drivers/gpu/drm/i915/i915_reg.h HomeHistoryAnnotateDownload only in i915_reg.h History log of /linux/stable/drivers/gpu/drm/i915/i915_reg.h Revision Date Author Comments (<<< Hide modified files) Add platform specific functions to convert the frequency in Hz to backlight PWM modulation frequency, and use them to initialize the backlight when the registers are not initialized by the BIOS. Our igt/tests/kms_frontbuffer_tracking already has support for this message. Firmware checker callback fn now returns errno rather than bool.